A Flexible Continuous-Time ΔΣ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures

摘要

A flexible continuous-time ΔΣ modulator that supports both low-pass and complex bandpass (CBP) architectures with the programmable bandwidths of 5 and 10 MHz is presented. By utilizing flexibility into both architectural level and core building blocks, scalable power consumption is obtained for each mode with desired performance. An amplifier topology with active feedforward, antipole splitting, and current reuse techniques is proposed for effective power reduction. A prototyped ΔΣ modulator in a 65-nm CMOS achieves a 65.1-/62.2-dB peak signal-to-noise-plus-distortion ratio (SNDR) with a 5-/10-MHz bandwidth in the LP architecture and a 62.9-/64.1-dB SNDR over a 5-/10-MHz signal band with a tunable center frequency of 4-6 MHz in the CBP architecture, respectively. The figure of merit is 0.21/0.23/0.36/0.24 pJ/conversion step for each mode with a power consumption of 3.1/4.8/4.2/6.3 mW by a 1.2 V supply voltage. The dynamic range is 73/65.8/74.3/74.2 dB. The active area is 0.39 mm2.