A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

摘要

A delta-sigma (ΔΣ) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm2 of die area and is implemented in a 0.18-Μm five-metal single-poly digital CMOS process.