A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS

摘要

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.