Design of a WSI Scale Parallel Processor for Intelligent Robot Control Based on a Dynamic Reconfiguration of Multi-Operand Arithmetic Units

摘要

A "restructurable(reconfigurable)parallel VISI processor" designed to minimize the operation delay time which can be generally used for various operations neces- sary for controlling an intelligent robot was proposed pre- viously by the authors. This processor is constructed by connecting a number of processor elements(PEs)in paral- lel under the assumption that one PE is integrated with one VLSI chip. In contrast to this, a method for constructing a Highly integrated processor by integrating several tens to 100 PEs on a single WSI is investigated in this paper.