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Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization

机译:对具有不同漏极掺杂分布的TFET上的双功函数,下重叠和异质栅电介质的影响研究,以评估和优化高频性能

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摘要

This manuscript presents a comparative study of different combination for the dual workfunction gate material, underlap and hetero gate dielectric tunnel field-effect transistors (TFETs). Their performances have been analyzed in terms of ON-state current, ambipolar behaviour and RF response along with different drain doping profile. For this, the Dual work function of gate provides enhancement in ON-state current by reducing the tunnel barrier width at source/channel interface. Whereas, the underlap of gate is done near to the drain region, helps in reduction of ambipolar conduction by creating deficiency of hole for the conduction, which is major hurdle for TFET. Further, the combinations of the dual workfunction and underlap give combine advantages of both such as improve ON-state current and suppressed ambipolar current. Apart from this, the combination of hetero gate dielectric dual workfunction under lapping leads to superior device performance in terms of ON-state current and ambipolar behaviour. The use of hetero gate dielectric and Gaussian doping profile with gate underlap reduces the gate to drain capacitance that also improves the RF parameters of the device.
机译:该手稿对双功函数栅极材料,叠底和异质栅介质隧道场效应晶体管(TFET)的不同组合进行了比较研究。已根据导通电流,双极性行为和RF响应以及不同的漏极掺杂曲线对它们的性能进行了分析。为此,栅极的双重功函数通过减小源/通道接口处的隧道势垒宽度来增强导通状态电流。而栅极的下重叠在漏极区附近完成,通过为导电造成空穴不足而有助于减少双极性导电,这是TFET的主要障碍。此外,双重功函数和欠重叠的组合给出了两者的组合优点,例如改善了导通电流和抑制了双极性电流。除此之外,在导通状态电流和双极性​​行为方面,异质栅极介电双重功函数在研磨条件下的组合可带来出色的器件性能。异质栅极电介质和高斯掺杂轮廓与栅极搭接的使用减少了栅极到漏极的电容,这也改善了器件的RF参数。

著录项

  • 来源
    《Superlattices and microstructures》 |2016年第8期|36-46|共11页
  • 作者单位

    Nanoscale Devices, Circuit and System Design Lab., Electronics and Communication Engineering Discipline, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, 482005, India;

    Nanoscale Devices, Circuit and System Design Lab., Electronics and Communication Engineering Discipline, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, 482005, India;

    Nanoscale Devices, Circuit and System Design Lab., Electronics and Communication Engineering Discipline, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, 482005, India;

    Nanoscale Devices, Circuit and System Design Lab., Electronics and Communication Engineering Discipline, PDPM Indian Institute of Information Technology Design and Manufacturing, Jabalpur, 482005, India;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Band to band tunneling; Dual material gate; Source pocket; Gate underlap; Hetero gate dielectric;

    机译:带对带隧道;双材料浇口;源袋;门重叠异质栅电介质;

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