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Design and simulation of oxide and doping engineered lateral bipolar junction transistors for high power applications

机译:用于大功率应用的氧化物和掺杂工程横向双极结型晶体管的设计和仿真

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摘要

In this paper, we propose new structures of lateral bipolar junction transistor (LBJT) on silicon on insulator (SOI) with improved performance. The proposed devices are lateral bipolar transistors with multi doping zone collector drift region and a thick buried oxide under the collector region. Calibrated simulation studies have revealed that the proposed devices have higher breakdown voltage than the conventional device, that too at higher drift doping concentration. This has resulted in improved tradeoff between the on-resistance and the breakdown voltage of the proposed devices. It has been observed that the proposed device with two collector drift doping zones and a buried oxide thick step results in ~190% increase in the breakdown voltage than the conventional device. The further increase in the number of collector drift doping zones from two to three has increased the breakdown voltage by 260% than the conventional one. On comparing the proposed devices with the buried oxide double step devices, it has been found that an increase of ~15-19% in the breakdown voltage is observed in the proposed devices even at higher drift doping concentrations. The use of higher drift doping concentration reduces the on-resistance of the proposed device and thus improves the tradeoff between the breakdown voltage and the on-resistance of the proposed device in comparison to buried oxide double step devices. Further, the use of step doping in the collector drift region has resulted in the reduction of kink effect in the proposed device. Using the mixed mode simulations, the proposed devices have been tested at the circuit level, by designing and simulating inverting amplifiers employing the proposed devices. Both DC and AC analyses of the inverting amplifiers have shown that the proposed devices work well at the circuit level. It has been observed that there is a slight increase in ON delay in the proposed device; however, the OFF delay is more or less same as that of the conventional device.
机译:在本文中,我们提出了在绝缘体上硅(SOI)上的横向双极型结型晶体管(LBJT)的新结构。所提出的器件是具有多掺杂区集电极漂移区和在集电极区下方的厚掩埋氧化物的横向双极晶体管。校准的仿真研究表明,所提出的器件具有比常规器件更高的击穿电压,在更高的漂移掺杂浓度下也是如此。这导致所提出的器件的导通电阻和击穿电压之间的折衷得到改善。已经观察到,所提出的具有两个集电极漂移掺杂区和掩埋氧化物厚台阶的器件导致击穿电压比常规器件增加〜190%。集电极漂移掺杂区的数量从两个进一步增加到三个,使击穿电压比传统的增加了260%。通过比较所提出的器件和掩埋氧化物双步器件,发现即使在较高的漂移掺杂浓度下,所提出的器件的击穿电压也增加了约15-19%。与掩埋氧化物双步器件相比,较高的漂移掺杂浓度的使用降低了所提出的器件的导通电阻,从而提高了击穿电压和所提出的器件的导通电阻之间的折衷。此外,在集电极漂移区中使用阶梯掺杂已导致所提出的器件的扭结效应降低。使用混合模式仿真,通过设计和仿真采用拟议器件的反相放大器,已在电路级对拟议器件进行了测试。反相放大器的直流和交流分析都表明,所提出的器件在电路级上工作良好。已经观察到,所提出的装置的ON延迟略有增加。然而,OFF延迟与常规设备的延迟大致相同。

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