ESD protection design on analog pin with very low input capacitancefor high-frequency or current-mode applications

摘要

An electrostatic discharge (ESD) protection design is proposed tonsolve the ESD protection challenge to the analog pins: fornhigh-frequency or current-mode applications, By including an efficientnpower-rails clamp circuit in the analog input/output (I/O) pin, thendevice dimension (W/L) of an ESD clamp device connected to the I/O padnin the analog ESD protection circuit can be reduced to only 50/0.5n(Μm/Μm) in a 0.35-Μm silicided CMOS process, but it can sustainnthe human body model (HBM) and machine model (MM) ESD level of up to 6nkV (400 V). With such a smaller device dimension, the input capacitancenof this analog ESD protection circuit can be significantly reduced tononly ~1.0 pF (including the bond-pad capacitance) for high-frequencynapplications