Clock-deskew buffer using a SAR-controlled delay-locked loop

摘要

A successive approximation register-controlled delay-locked loopn(SARDLL) has been fabricated in a 0.25-Μm standard n-well DPTM CMOSnprocess to realize a fast-lock clock-deskew buffer for long distancenclock distribution. This DLL adopts a binary search method to shortennlock time while maintaining tight synchronization between input andnoutput clocks. The measured lock time of the proposed SARDLL is withinn30 clock cycles at 100-MWz clock input. The power dissipation is 3.3 mWn(not including off-chip driver's) at a 1.1-V supply voltage while thenmeasured rms and peak-to-peak jitter are 11.3 ps and 95 Μs,nrespectively