Delay circuit of delay-locked loop circuit and delay-locked loop circuit

摘要

A delay circuit of a delay-locked loop (DLL) circuit according to embodiments of the present invention includes a phase separator, a logic gate, and a delay line circuit. The phase separator separates the phases of the reference clock signal and outputs a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees. The logic gate outputs the delayed reference clock signal by delaying the second reference clock signal. The delay line circuit includes a plurality of delay cells connected in cascade, and delays the first reference clock signal and the delay reference clock signal based on a control code set to correspond to the delay of one logic gate included in the delay cells. A first delayed clock signal and a second delayed clock signal having a delay amount of