Delay-locked loop circuits semiconductor memory devices and methods of operating delay-locked loop circuits

摘要

The present invention relates to a delay-locked loop (DLL) circuit of a semiconductor device, which is capable of preventing a duty error of divided clock signals and a recovery clock signal, and a semiconductor device and an operation method thereof. According to the present invention, the DLL circuit of a semiconductor device comprises: a first duty cycle corrector responding to first correction codes to adjust at least a part of duty among first to fourth divided clock signals having multi-phase generated based on a reference clock signal so as to provide first to fourth corrected clock signals; a second duty cycle corrector responding to a second correction code to adjust at least a part of delay of second to fourth delayed clock signals among first to fourth delayed clock signals so as to provide first to fourth source clock signals; a clock tree providing the first to fourth source clock signals into the semiconductor device as first to fourth full-wave clock signals; a first duty cycle detector detecting the duty of the first full-wave clock signal to generate a first sub correction code among the first correction codes, and detecting first and second recovery clock signals recovered based on the first to fourth full-wave clock signals to generate the second correction code; and a second duty cycle detector detecting the duty of the second full-wave clock signal to generate a second sub correction code among the first correction codes.