A 1-V, 8-bit successive approximation ADC in standard CMOS process

摘要

A 1-V 8-bit 50-kS/s successive approximation analog-to-digitalnconverter (ADC) implemented in a conventional 1.2-Μm CMOS process isnpresented. Low voltage, large signal swing sample-and-hold, andndigital-to-analog conversion are realized based on inverting op-ampnconfigurations with biasing currents added to the op-amp negative inputnterminal so that the op-amp input common-mode voltages can be biasednnear ground to minimize the supply voltage. At the same time, the inputnand output quiescent voltages can be set at half of the supply rails. Anlow-voltage latched comparator is realized based on the current-modenapproach. The entire ADC including all the digital circuits consumesnless than 0.34 mW. An effective number of bits of 7.9 was obtained for an1-kHz 850-mV peak-to-peak input signal