An 80/20-MHz 160-mW multimedia processor integrated with embeddedDRAM, MPEG-4 accelerator and 3-D rendering engine for mobileapplications

摘要

A low-power multimedia processor for mobile applications isnpresented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHznhardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visualnSP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, andnperipheral blocks are integrated together on a single chip, MPEG-4 SP@L1nvideo decoding and 3-D graphics rendering with a 16-b depth-buffernalpha-blending double-buffering and gouraud-shading features at 2,n2-Mpolygons/s speed are realized with the help of the dedicated hardwarenaccelerators/ The architecture of the processor is optimized in terms ofnpower consumption and performance, and various low-power circuitntechniques are adopted in each hardware block. The chip is implementednusing 0.18-Μm embedded memory logic (EML) technology. Its area is 84nmm2, and power consumption is 160 mW when all of thenfunctions are activated