A 7.1-GB/s low-power rendering engine in 2-D array-embedded memorylogic CMOS for portable multimedia system

摘要

A single-chip rendering engine that consists of a DRAM framenbuffer, a SRAM serial access memory, pixel/edge processor array and 32-bnRISC core is proposed for low-power three-dimensional (3-D) graphics innportable systems. The main features are two-dimensional (2-D)nhierarchical octet tree (HOT) array structure with bandwidthnamplification, three dedicated network schemes, virtual page mapping,nmemory-coupled logic pipeline, low-power operation, 7.1-GB/s memorynbandwidth, and 11.1-Mpolygon/s drawing speed. The 56-mm2nprototype die integrating one edge processor, eight pixel processors,neight frame buffers, and a RISC core are fabricated using 0.35-ΜmnCMOS embedded memory logic (EML) technology with four poly layers andnthree metal layers. The fabricated test chip, 590 mW at 100 MHz 3.3 Vnoperation, is demonstrated with a host PC through a PCI bridge