A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

摘要

A 10-Gb/s phase-locked clock and data recovery circuitnincorporates an interpolating voltage-controlled oscillator and anhalf-rate phase detector. The phase detector provides a linearncharacteristic while retiming and demultiplexing the data with nonsystematic phase offset. Fabricated in a 0.18-Μm CMOS technology innan area of 1.1×0.9 mm2, the circuit exhibits an RMSnjitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock,nand a bit-error rate of 1.28×10-6, with random dataninput of length 223-1. The power dissipation is 72 mW from an2.5-V supply