A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibratedΣ-Δ frequency synthesizer

摘要

This paper describes a new sigma-delta (Σ-Δ) frequencynsynthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK)nmodulation. The key innovation is an automatic calibration circuit whichntunes the phase-locked loop (PLL) response to compensate for processntolerance and temperature variation. The availability of this newncalibration method allows the use of precompensation techniques tonachieve high data rate modulation without requiring factory calibration.nThe calibration method can be applied to GFSK/GMSK modulation and alsonM-ary FSK modulation. The PLL, including 1.8-GHz voltage controllednoscillator (VCO), Σ-Δ modulator, and automatic calibrationncircuit, has been implemented in a 0.6-Μm BiCMOS integrated circuit.nThe test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s usingn4-FSK