A CMOS GSM IF-sampling circuit with reduced in-channel aliasing

摘要

A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-Μm CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.