METHOD FOR REDUCING POWER CONSUMPTION IN LOW-POWER CMOS INVERTER OR CMOS INVERTER CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce a power consumption amount of a CMOS circuit by providing a circuit that is provided with plural FETs and a means which prevents current from simultaneously flowing through the FETs. SOLUTION: A pair of MP2 AND MN2 devices 16 and 18 is serially connected to MP1 AND MN1 devices 12 and 14. When an input signal VIN gradually starts to rise during transition from low to high, and a buffer 22 converts it into a fast rise pulse that appears on an output side and operates as a circuit which forms a waveform through this. The fast pulse cuts the MP2 before the MP1/MN1 inverters reach a trip point and flow of passing current is interrupted. The same matter occurs when an input signal transits from high to low. The buffer 22 cuts the MN2 before the MP1/MN1 inverters reach the trip point, also in this case, the negative transition of an input signal reduces the flow of passing current.