A 400-MHz Random-Cycle Dual-Port Interleaved DRAM (D{sup}2RAM) With Standard CMOS Process

摘要

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D{sup}2RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D{sup}2RAM fabricated by a 0.15-μm standard CMOS process.