A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology

摘要

This paper presents a digital phase-locked loop (DPLL) used for GHz clock generation in large digital systems with $>100times$ range of operating frequency. The DPLL uses phase selection and interpolation as the digital-controlled oscillator (DCO). A bandwidth-tracking technique that uses replica delay cells in the DCO and the phase detector (PD) is introduced to enable stable operation across the frequency range without calibration. Measurement results show that the DPLL achieves an output frequency up to 1.8 GHz in a 65-nm CMOS technology. Nearly constant damping factor and the tracking of the loop bandwidth to reference frequency are shown with a dynamic sweep of 8 $times$ reference frequency range (from 28 MHz to 225 MHz with core frequency of 3.6 GHz).