A CMOS digital phase-locked loop for nanometer-scale techonology.

摘要

Digital implementations of phase-locked loops (DPLLs) have emerged as an attractive alternative as variability and poor analog characteristics of devices plague designs in manometer CMOS process. With fully-digital loop filters, designs can be portable and easily programmable for operation across a wide range of operating frequencies and process corners, while the design of the digital-controlled oscillator (DCO) and the phase detector dictates the signal quality and usually remains relatively analog-intensive and challenging.;We propose a DPLL design for clock generation in large digital systems. A 9-bit interpolator-based DCO is used in the proposed design for low jitter performance and wide operating frequency range. The use of an integer divider in the loop filter greatly relaxes the trade-off between the steady-state dithering jitter and the resolution requirement on the DCO. The phase selection is based on a token-passing technique with an asynchronous control block using self-reset circuits to speed up the operation and to reach gigahertz of operation. With the ability to dynamically sweep the output frequency from 3.5MHz to 1.8GHz, the proposed design is suitable for Dynamic Voltage and Frequency Scaling (DVFS) and spread-spectrum I/O applications. Bandwidth-tracking ability is achieved with the use of replica delay line in the time-to-digital converter (TDC) as the phase detector. The resulting loop characteristic depends only on the implementation of the digital loop filter. Without calibration, the empirical results show a near constant damping factor and a bandwidth that tracks with input frequency over 2x of core oscillation frequencies (2.5CHz-5.0GHz) and reference frequencies from 19.5MHz to 312MHz. Nonlinear phase detector transfer curve enables low jitter and fast loop response with fewer TDC levels.;The prototype is designed and implemented with 65-nm CMOS technology with the core area of 800 mum x 700mum. The design consumes 220mW at 1.6GHz with the measured rms/pp jitter of 2.63/22.2ps.