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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An $80imes25$ Pixel CMOS Single-Photon Sensor With Flexible On-Chip Time Gating of 40 Subarrays for Solid-State 3-D Range Imaging
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An $80imes25$ Pixel CMOS Single-Photon Sensor With Flexible On-Chip Time Gating of 40 Subarrays for Solid-State 3-D Range Imaging

机译: $ 80 times25 $ 具有灵活片上时间门控功能的像素CMOS单光子传感器固态3-D范围成像的子阵列

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摘要

A CMOS solid-state 3-D range imager that uses short (similar to 110 ps) laser pulses and a novel flexible time gating scheme for a single-photon avalanche diode (SPAD) array is presented. The array is divided into 40 subarrays for which a narrow (<0.8 ns) time gating position can be set and scanned independently. The imager can be set to measure multiple regions of interest by means of the flexible time gating of the subarrays. The time gating for each of the subarrays is selected separately with an on-chip delay-locked loop (DLL) block that has 240 outputs and a delay grid of similar to 100 ps. The prototype has 80 x 25 pixels overall with 10x5 pixel subarrays. The fill factor of the sensor area is 32%. A 3-D range image is demonstrated at similar to 10 frames/s with centimeter-level precision in the case of passive targets within a range of similar to 4 m and a field of view of 18 degrees x 28 degrees, requiring an average active illumination power of only 0.1 mW.
机译:提出了一种使用短(类似于110 ps)激光脉冲的CMOS固态3-D范围成像器,以及针对单光子雪崩二极管(SPAD)阵列的新颖灵活的时间门控方案。该阵列分为40个子阵列,可以为它们设置窄的(<0.8 ns)时间选通位置并独立扫描。可以通过子阵列的灵活时间选通将成像器设置为测量多个感兴趣区域。每个子阵列的时间选通分别通过片上延迟锁定环(DLL)块进行选择,该块具有240个输出和一个类似于100 ps的延迟网格。原型总共具有80 x 25像素,并带有10x5像素子阵列。传感器区域的填充率为32%。对于被动目标,在类似于4 m的范围内且视野为18度x 28度的情况下,需要以平均主动模式拍摄,以厘米级精度以接近10帧/秒的速度演示3-D范围图像。照明功率仅为0.1 mW。

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