A 14-ns 14-Mb CMOS DRAM with 300-mW active power

摘要

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7- mu m L/sub eff/ CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm*6.38-mm chip, organized as either 512 K word*8 b or 1 M word*4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V/sub cc/ and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V/sub cc/ to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time.