The super-diode-DRAM (SD-DRAM) — A comparative approach for CMOS memory cell to obtain low power consumption and read/write access time

摘要

In today's era, low power VLSI research became an intensified quarter in nanometric regimes. As the technology size shrinks down, the leakage power becoming an overwhelming issue in every facet. Most appropriate key element to diminish leakage power from CMOS memory cell is to scale down the supply voltage and frequencies. DRAM consumes more power compared to SRAM, so reducing power becoming a challenging issue. The PDP factor need to be optimized as in CMOS memory cell exhibits two conflicting gauge between power dissipation and circuit delay. In this paper we introduced a super Diode DRAM cell, which can efficiently reduce power dissipation and a satisfactory PDP value obtained without any hurdle. The super Diode DRAM (SD-DRAM) cell, incorporated a gated diode which is responsible to store charge for Write/Read operation instead of any capacitor that used in mainstream designing approach such as 1T, 3T, 4T DRAM cell; which leads to a better performance in the area of power consumption. Through this research work, a comparative study of power, delay and PDP also deliberate to emphasize the performance of proposed SD-DRAM designing concept.