Disilane-based cyclic deposition/etch of Si, Si:P and Si_(1-y)C_y: P layers: II. The CDE features

摘要

We have developed innovative cyclic deposition/etch (CDE) processes in order to grow Si, Si:P and Si_(1-y)C_y:P raised sources and drains (RSDs) on patterned wafers. A Si_2H_6 + PH_3 + SiCH_6 chemistry was used for the 550 ℃ growth steps. Meanwhile, the selective etch of poly-crystalline layers on dielectrics was conducted at 600 ℃ with HC1 + GeH_4. We have first studied the specifics of those isobaric (P = 20 Torr) CDE processes on bulk, blanket Si(0 0 1) substrates. CDE-grown Si, Si:P and Si_(1-y)C_y: P) layers were high crystalline quality and smooth, although these also contained 2-3% of Ge. Due to the preferential incorporation of P atoms in the lattice, the 'apparent' substitutional C content was higher for intrinsic than for in situ phosphorous-doped layers (1.29% versus 1.17% and 1.59% versus 1.47% for the two SiCH_6 mass-flows probed). The atomic P concentration in our Si_(1-y)C_y:P layers was close to 2.6 × 10~(20) cm~(-3), versus 2.1 × 10~(20) cm~(-3) in the Si:P layers. The Si, Si:P and Si_(1-y)C_y(:P) thickness deposited in each CDE cycle decreased linearly as the HCl+GeH_4 etch time increased, with the 'equivalent' etch rate (i.e. the slope of this linear decrease) being lower in intrinsic than in in situ doped layers. Higher C contents resulted in lower 'equivalent' etch rates. A CDE strategy suppressed the surface roughening occurring for high C content, several tens of nm thick Si_(1-y)C_y: P layers grown in one step only. We have then calibrated, for 19-23 nm thick CDE-grown Si, Si:P and Si_(1-y)C_y:P RSDs, the HC1 + GeH_4 etch time per step necessary to achieve full selectivity on patterned silicon-on-insulator substrates. Selectivity was obtained for intrinsic Si once 180 s etch steps were used. Longer etch times were needed for Si:P and especially Si_(1-y)C_y: P (270 and 315 s/CDE cycle, respectively). The resulting S/D areas were rather smooth and slightly facetted, but the un-protected poly-Si layers sitting on top of the gate stacks were completely removed with these etch times.