Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits

摘要

The rising trend of globalization in integrated circuits (ICs) design and fabrication process has increased their vulnerability against malicious intrusions and alterations. Such modifications, also referred as Hardware Trojans (HTs), can lead to highly detrimental consequences like causing an IC to subvert normal operation, leak sensitive information or inducing denial of service (DoS). The vulnerability analysis of ICs against the malicious intrusions with conventional design-time testing and exhaustive simulations is computationally intensive, and it takes substantial resources and time for all-encompassing verification. To overcome these limitations, we propose a formal framework, based on gate-level side channel parameters, for a-priori assessment of IC vulnerability against HTs at the early stages of the design. This work employs formal modeling of the IC behavior in terms of switching power, propagation delay and leakage in order to examine the impact of malicious intrusions. We used the bounded model checker nuXmv, to formally verify and analyze the identified properties, owing to its inherent ability to handle real numbers and its support for analyzing infinite state domains. The vulnerabilities of ICs against HTs, and their effects on the IC nodes are assessed by analyzing linear temporal logic (LTL) properties, which are subsequently rendered into behavioral traces. We demonstrate the effectiveness of our approach on a set of ISCAS benchmarks. (C) 2018 Elsevier B.V. All rights reserved.