A Novel Approach for X-filling and Reordering Test Vectors for Power Reduction

摘要

Optimization of testing power is a significant task to be carried out in digital circuit design. During testing, the power dissipation will be high due to very high number of toggles between test vectors. Hence power minimization is significant during testing. X bits in the test vectors are identified and then X bits are replaced with their appropriate values. The filled vector set is next reordered. In this study, Kruskal based approach is proposed for reordering the vector to minimize the number of toggles and hence power consumption. It is experimented with ISCAS89 benchmark circuits, generated from MINTEST to validate our study.