一种基于海明排序进行无关位填充的低功耗测试向量优化方法

摘要

集成电路在测试过程中的测试功耗通常会远远高于集成电路正常工作时的功耗,而过高的测试功耗可能会造成电路损坏或是芯片烧毁.为了降低测试功耗,提出了一种基于海明排序进行无关位填充的低功耗测试向量优化方法.首先,对测试集中的测试向量按照无关位含量由多到少进行排序;然后,将测试向量按照海明距离由小到大进行排序;最后,对排序后的测试集进行无关位的合理填充,使得测试向量之间的相关性增大,从而降低测试功耗.以ISCAS'85国际标准电路作为测试对象进行,结果表明,相比于使用优化前的测试集,运用优化后的测试集明显降低了测试功耗.%The test power consumption in the process of integrated circuit testing is usually much higher than the normal power consumption of the integrated circuit.However,the high test power consumption may cause the circuit to be damaged or the chip to be burned.An optimization method of low power test vectors based on Hamming sorting for X bits padding was proposed to reduce the test power consumption.Firstly,the test vectors in the test set are ranged from high X bits to low X bits.Then,the test vectors are sorted in ascending order according to the Hamming distance.Finally,the test power consumption is reduced by padding X bits for the sorted test set reasonably,which increases the correlation between test vectors.The ISCAS'85 standard circuit was used as the test object.The experimental results show that compared with using the non-optimized test set,the test power consumption is reduced obviously with the optimized test set.