Hybrid CMOS thin-film devices based on solution-processed CdS n-TFTs and TIPS-Pentacene p-TFTs

摘要

Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The n- and p-type thin film transistors (TFTs), inverters, and NAND gate devices were fabricated using photolithography-based techniques. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100℃) and scalable design. The integrated n-and p-type devices show saturation mobilities of 15 and 0.02 cm~2/V s, respectively. The inverters exhibited a DC gain of ≈52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V_(DD)/2.