Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

摘要

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, highspeed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of 10 channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment. (c) 2006 Elsevier B.V. All rights reserved.