A scan compression architecture for a design for testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset of the pins. The first scan architecture is selectively enabled for executing a scan test with a low time. The second scan architecture is for executing a scan test with high parallelism.
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