2値・多値融合論理設計に基づく高性能LSIシステムに関する研究

摘要

This paper presents high-performance LSI systems based on binary/multiple-valued fused logic design. We design and evaluate Field-Programmable Digital Filter (FPDF) LSIs, which employ redundant arithmetic algorithms for faster operation and multiple-valued current-mode logic for high-density low-power implementation. We demonstrate that area and power of the prototype FPDF can be reduced significantly in comparison with the standard binary logic implementation. We also propose a high-level design method of LSI systems based on binary/multiple-valued fused logic. To implement the proposed design method, we develop a standard-cell library containing multiple-valued logic circuit cells. This paper demonstrates the potential of the proposed design flow through an experimental synthesis of a 32-bit parallel multiplier based on binary/multiple-valued fused logic. Furthermore, this paper presents a new type of binary/multiple-valued fused logic circuit using Single-Electron-Transistor (SET) logic gate family. The proposed logic gate family can implement practical circuits by employing the high-functionality of the SET. As an example, we present a new circuit design of content-addressable memories using SETs that can reduce cell area, total transistor count, power and delay in comparison with traditional CMOS technologies.%本論文では，2値・多値融合論理LSIシステムの 実現に向けて，（1）MV-CML回路によるFPDFを 提案し，その設計・試作・評価を通し，多値論理集積 回路を利用した大規模なLSIシステムの動作を実証 するとともに配線問題に対する有効性を明らかにした.また，（2）効率的な設計手法として，2値・多値 融合論理回路のハイレベル設計フローを提案し，2値・多値融合論理乗算器の設計を通してその有用性 を示した．さらに，次世代の高性能LSIシステムの 実現に向けて，（3）SETを用いた論理ゲートファミ リを体系化するとともに，これを応用した算術演算 回路の設計例を示した．また，SETを用いたCAM を提案し，その基本回路の試作と動作検証を行い， 従来のCAMと比べて高性能なCAMを実現できる ことを明らかにした．