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A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm

机译:使用LMS自适应算法的高可扩展并行基于尖峰的数字神经形态架构,用于高阶冷杉滤波器

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This brief presents a highly scalable parallel neuromorphic architecture to efficiently compute high-order adaptive FIR filters using a least mean square (LMS) algorithm. This has been achieved by eliminating critical paths because they critically affect the scalability of advanced parallel architectures. Here, the scalability is defined in terms of number of taps and bit-length. On the computation of high-order adaptive FIR filters, the multiplication is the most demanding operation. Therefore, we have made intensive efforts to create a compact new neural multiplier by improving the design and hardware implementation of an existing neural multiplier. The resulting multiplier requires 50 % fewer synapses, 40 % fewer neurons, 30 % fewer area resources and 26 % fewer clock cycles compared with the existing neural multiplier, respectively. The efficient implementation of the proposed multiplier has allowed us to eliminate critical paths significantly and thus the bit-length can be easily increased to guarantee the convergence performance when high-order adaptive filters are processed. To demonstrate its effectiveness, the proposed multiplier was included in the neuromorphic architecture to support high-order adaptive FIR filters. In addition, we employ the time multiplexing technique to maximize the utilization of the proposed neural multiplier by performing filter processing and the adaptive process because multiplication is involved in both. We mainly use this strategy to eliminate critical paths and reduce the area consumption by implementing a large number of taps. The proposed neuromorphic architecture was implemented on the Kintex-7 Field Programmable Gate Array (FPGA) development kit to validate its performance. Our results demonstrate that the neuromorphic architecture is capable of processing higher adaptive FIR filters compared with previously reported solutions. This potentially allow its practical use in many advanced digital signal processing applications such as acoustic echo cancellers, active noise control, channel equalization and system identification. (C) 2018 Elsevier B.V. All rights reserved.
机译:本简介介绍了一种高度可扩展的并行神经形态架构,可使用最小均方(LMS)算法有效地计算高阶自适应FIR滤波器。这是通过消除关键路径来实现的,因为它们会严重影响高级并行体系结构的可伸缩性。在此,可扩展性是根据抽头的数量和位长来定义的。在高阶自适应FIR滤波器的计算中,乘法是最苛刻的操作。因此,我们通过改进现有神经乘法器的设计和硬件实现,为创建紧凑的新型神经乘法器付出了巨大的努力。与现有的神经乘法器相比,所得的乘法器分别需要少50%的突触,少40%的神经元,少30%的区域资源和少26%的时钟周期。所提出的乘法器的有效实现使我们能够显着消除关键路径,因此当处理高阶自适应滤波器时,可以很容易地增加位长以保证收敛性能。为了证明其有效性,将拟议的乘法器包括在神经形态架构中以支持高阶自适应FIR滤波器。此外,我们采用时分多路复用技术通过执行滤波处理和自适应过程来最大化所提出的神经乘法器的利用率,因为两者都涉及到乘法。我们主要使用这种策略来消除关键路径并通过实现大量抽头来减少面积消耗。拟议的神经形态架构已在Kintex-7现场可编程门阵列(FPGA)开发套件上实施,以验证其性能。我们的结果表明,与以前报道的解决方案相比,神经形态结构能够处理更高的自适应FIR滤波器。这有可能使其实际应用在许多高级数字信号处理应用中,例如回声消除器,有源噪声控制,信道均衡和系统识别。 (C)2018 Elsevier B.V.保留所有权利。

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