首页> 外文期刊>IEEE Transactions on Neural Networks >A CMOS analog adaptive BAM with on-chip learning and weight refreshing
【24h】

A CMOS analog adaptive BAM with on-chip learning and weight refreshing

机译:具有片上学习和权重刷新功能的CMOS模拟自适应BAM

获取原文
获取原文并翻译 | 示例

摘要

The transconductance-mode (T-mode) approach is extended to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. The demonstration vehicle used is a 5+5-neuron bidirectional associative memory (BAM) prototype fabricated in a standard 2- mu m double-metal double-polysilicon CMOS process. Mismatches and nonidealities in learning neural hardware are not supposed to be critical if on-chip learning is available, because they will be implicitly compensated. However, mismatches in the learning circuits themselves cannot always be compensated. This mismatch is specially important if the learning circuits use transistors operating in weak inversion. The authors estimate the expected mismatch between learning circuits in the BAM network prototype and evaluate its effect on the learning performance, using theoretical computations and Monte Carlo HSPICE simulations. These theoretical predictions are verified using experimentally measured results on the test vehicle prototype.
机译:跨导模式(T模式)方法得到扩展,以实现模拟连续时间神经网络硬件系统,以包括片上Hebbian学习和片上模拟权重存储功能。使用的演示工具是采用标准2微米双金属双多晶硅CMOS工艺制造的5 + 5-神经元双向联想存储器(BAM)原型。如果可以进行片上学习,则学习神经硬件中的不匹配和非理想性并不重要,因为它们将得到隐式补偿。但是,学习电路本身的失配不能总是得到补偿。如果学习电路使用弱反相工作的晶体管,则这种失配尤为重要。作者使用理论计算和蒙特卡洛HSPICE仿真来估计BAM网络原型中学习电路之间的预期失配,并评估其对学习性能的影响。这些理论预测是通过在测试车辆原型上的实验测量结果来验证的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号