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3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead

机译:3D-ProWiz:具有节能和光学接口的3D DRAM架构,减少了数据访问开销

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This paper introduces , which is a high-bandwidth, energy-efficient, optically-interfaced 3D DRAM architecture with fine grained data organization and activation. integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus to individual subarrays using TSVs and fanout buffers enables to use smaller dimension subarrays without significant area overhead. The use of TSVs at subarray-level granularity eliminates the need to use slow and power hungry global lines, which in turn reduces the random access latency and activation-precharge energy. yields the best latency and energy consumption values per access among other well-known 3D DRAM architectures. Experimental results with PARSEC benchmarks indicate that achieves 41.9 percent reduction in average latency, 52 percent reduction in average power, and 80.6 percent reduction in energy-delay product (EDP) on average over DRAM architectures from prior work.
机译:本文介绍,这是一种具有细粒度数据组织和激活功能的高带宽,高能效,光接口3D DRAM架构。集成了数据阵列的子库级3D分区,以实现细粒度的激活和更大的内存并行性。使用TSV和扇出缓冲器将内部存储器总线路由到各个子阵列的新颖方法可以使用较小尺寸的子阵列,而不会产生较大的面积开销。以子阵列级粒度使用TSV无需使用慢速且耗电的全局线路,从而减少了随机访问延迟和激活预充电能量。在其他众所周知的3D DRAM架构中,每次访问产生最佳的延迟和能耗值。 PARSEC基准测试的结果表明,与之前的工作相比,与DRAM架构相比,平均延迟平均降低了41.9%,平均功率降低了52%,能量延迟产品(EDP)降低了80.6%。

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