机译:低级逻辑故障测试ASIC仿真环境
School of Engineering and Physics, University of the South Pacific, Suva 19128, Fiji;
Center for Information and Communication Technology, University of Trinidad and Tobago, Arima, Trinidad, West Indies;
Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103, USA,School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada;
School of Engineering and Technology, Kaziranga University, Jorhat, Assam 785006, India;
Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103, USA;
Application-specific integrated circuit; built-in self-testing; circuit under test; intellectual property cores; low-level logic fault test simulation; test pattern generator;
机译:使用CMOS工艺表现出场氧化物泄漏的ASIC中总剂量引起的逻辑故障的最坏情况测试向量
机译:基于剂量的基于单元的ASIC组合电路中逻辑故障的故障建模和最坏情况测试向量
机译:通过嵌入式二进制异步计数器周围逻辑的内置可测试性,使ASIC测试序列最小化
机译:基于单元的ASIC组合电路中引起的逻辑故障的总剂量最坏情况测试向量
机译:通过I(DDQ)测试进行故障仿真和故障建模。
机译:变形翼尖驱动系统的基于模糊逻辑的控制:设计数值模拟和风洞实验测试
机译:逻辑验证和等效检查的测试选择以及故障仿真的使用