Look ahead pattern generation and simulation including support for parallel fault simulation in LSSD/VLSI logic circuit testing

摘要

Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at the end of each Tester Loop (TL) simulation: (1) restore to the state just prior to the current simulated Tester Loop and advance the pattern generators one state if an ineffective Tester Loop was found or (2) advance the pattern generators one state (from the end of the Tester Loop) if an effective Tester Loop was encountered. This basic technique can be modified to support parallel fault simulation by defining the pattern generator state at the start of the next tester loop (TL) state (TL.sub.n+1) to be one state advanced from the pattern generator state at the START of TL.sub.n. The pattern generator state for the start of all future TLs can be determined and parallel fault simulation is supported.