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Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
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机译:用于ATPG(自动测试图案生成)的智能捕获和基于扫描的集成电路的故障仿真
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摘要
A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network. The method comprises compiling the scan-based integrated circuit into a sequential circuit model; specifying input constraints on the scan-based integrated circuit during a shift and capture operation; specifying a clock grouping to map the N clock domains into G clock domain groups, where NG1; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints.
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