Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

摘要

In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.