DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories

摘要

In this paper, a data sensitive write circuit is presented to decrease the Write attempt error in STT-RAM memories. CMOS technology presents a myriad of challenges to system designers in the form of soft error reliability, volatility, power consumption, and scalability. SIT-RAM (Spin Transfer Torque RAM) is one of promising non-volatile memory whose write error occurs basically due to fabrication process fluctuation. These problems which happen in different current densities made a key drawback in STT-RAM memory technologies. This paper addresses this problem and provides a solution for the drawback. A continuous and dynamic method along with the dual source approach is proposed and optimizations in physical characteristics of transistors is performed. The proposed technique can be classified into two major sections. The first section comprises of a thermal assisted circuit designed to decrease the asymmetric behaviour while writing the two states 0 and 1. A dynamic write current injector designed to hasten the write operation constitutes the subsequent section. In order to validate the design, a comparison has been made between the results of several functional simulations performed on DYSCO and the results of existing related studies. Using physical parameters optimization, we achieved WER reduction, write performance improvement and power gain. On average 27.17% improvement of write time latency is achieved with bounded 11% area overhead. (C) 2019 Elsevier B.V. All rights reserved.