首页> 外文期刊>Microprocessors and microsystems >Design and simulation of priority based dual port memory in quantum dot cellular automata
【24h】

Design and simulation of priority based dual port memory in quantum dot cellular automata

机译:量子点元胞自动机中基于优先级的双端口存储器的设计与仿真

获取原文
获取原文并翻译 | 示例

摘要

Design of dual port memory in QCA is an interesting field of study due to concurrent access of data from different ports, although the solution of the data conflict is a changeling task. However, Dual port memory design in QCA is reported in this paper. The architecture is based on the data priority. Priorities of the two ports are generated from the control logic block. Priority bit is required for conditions when the same memory location is requested by both of the ports and at least one operation is the write operation. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read-Write, Write-Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., the request for concurrent Read-Write or Write-Write operation. When the same memory location is selected, only the signal of the prior port is allowed and of other port is discarded. While the read operation is requested for both the port at same or different memory locations, have no data conflicts and both the ports are allowed to perform read operation. In the proposed architecture, to overcome data conflicts signals of the port having less priority are totally discarded. Significant results of Priority-based 4 x 4 dual port memory are depicted in terms of area and delay. The area, delay, and energy dissipation of Dual port QCA SRAM macro cell are 0.61 mu m(2), 2.0 clock cycles, and 393.9 meV, respectively. A comparative study of the proposed dual port memory in QCA, single port memory in QCA and dual port memory in CMOS are also performed in this work. The result explored that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory in terms of area-delay-energy. (C) 2019 Published by Elsevier B.V.
机译:由于可以同时访问来自不同端口的数据,因此QCA中双端口内存的设计是一个有趣的研究领域,尽管解决数据冲突的任务非常艰巨。但是,本文报告了QCA中的双端口内存设计。该体系结构基于数据优先级。这两个端口的优先级是从控制逻辑模块生成的。当两个端口都请求相同的存储位置并且至少一个操作是写操作时,需要使用优先级位。双端口存储器的功能是通过并行输入输出数据线并行访问存储器阵列来实现的。读写冲突通过优先级位解决。仅当两个端口都请求相同的存储位置访问时,即同时进行读写操作时,才唯一计算优先级。当选择相同的存储位置时,仅允许先前端口的信号,而其他端口的信号则被丢弃。虽然请求在相同或不同存储位置的两个端口进行读取操作,但没有数据冲突,并且两个端口都可以执行读取操作。在所提出的架构中,为了克服数据冲突,优先级较低的端口的信号被完全丢弃。基于优先级的4 x 4双端口内存的显着结果以面积和延迟表示。双端口QCA SRAM宏单元的面积,延迟和能量耗散分别为0.61μm(2),2.0个时钟周期和393.9 meV。这项工作还对建议的QCA中的双端口存储器,QCA中的单端口存储器和CMOS中的双端口存储器进行了比较研究。结果探索了建议的双端口存储器相对于QCA单端口存储器以及CMOS双端口存储器在面积延迟能量方面成比例地有效。 (C)2019由Elsevier B.V.发布

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号