Implementation of STAP algorithms on IBM SP2 and on ADSP 21062 dual digital signal processor systems

摘要

Space-time adaptive processing (STAP) is a well-known technique in the area of air borne surveillance radars, which is used to detect weak target returns embedded in strong ground clutter, interference, and receiver noise. Data processing for STAP refers to a 2D adaptive iterative algorithm which attenuates unwanted signals by placing nulls in the frequency domain with respect to their direction of arrival and/or Doppler frequencies. Most STAP applications are highly compute-intensive and are required to operate in real-time. Parallel computing is a method used to satisfy the computational requirements of real-time STAP while increasing the flexibility and scalability of radar signal processing systems. However, efficient parallelization of STAP algorithm, which consists of several different algorithms such a fast Fourier transform, QR factorization and beam-forming requires lot of optimizations, both at code level and at execution time level. The STAP algorithm is highly signal processing oriented and hence executes efficiently on digital signal processor (DSP)-based systems. In this work, we developed a parallel STAP algorithm on an IBM SP2 parallel computing system and on ADSP 21062 Dual-DSP system. With eight processors, IBM SP2 system gives a speed-up of only 2.4. The low speed-up can be attributed to the large volume of data movement across the tasks and across the processors. We also implemented the STAP algorithm on a dual-DSP system. The dual-DSP system is based on ADSP 21062 processor that operates at 40 MHz clock frequency. Due to large internal and shared memories, the overhead due to data movement across the tasks and across processors is very low and the results show that the speed-up with two processors is 1.9.