A pixel cache architecture with selective placement scheme based on z-test result

摘要

Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.