(PIP)-I-2: A novel low-latency Programmable Pipeline Image Processor

摘要

This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called (PIP)-I-2. The (PIP)-I-2 is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the (PIP)-I-2 enables it to perform a wide range of image pre-processing tasks directly on a pixel stream. The versatility of the (PIP)-I-2 is demonstrated through three image processing algorithms mapped onto the architecture, implemented in an FPGA-based platform. The obtained results show that the (PIP)-I-2 can achieve up to 129 fps in Full HD 1080p and 32 fps in 4K 2160p what makes it suitable for modern high-definition applications. (C) 2015 Elsevier B.V. All rights reserved.