机译:使用古代吠陀数学进行阶乘计算的高速低功耗电路的ASIC设计
School of VLSI Technology, Bengal Engineering and Science University, Shibpur, Howrah 711103, West Bengal, India;
Department of Electronics and Communication Engineering, JIS College of Engineering, Kalyani 741235, India;
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India;
Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University, Shibpur, Howrah 711103, West Bengal, India;
vedic multiplier; incrementer; zero detectors; decrementer; factorial design; high speed;
机译:基于吠陀数学的复数乘法器高速ASIC设计
机译:基于吠陀数学的高速低功耗处理器32位乘法器设计
机译:一种有效的低功耗乘法器的设计:可逆与古代吠陀方法相结合
机译:基于古代吠陀数学的吠陀平方计算器的鲁棒高速ASIC设计
机译:用于高速低功耗模数转换器的集成电路设计技术和传感器接口电路的片上校准
机译:高速调频原子力显微镜的宽带低延迟锁相环电路设计的定量比较
机译:基于古印度吠陀数学的32位乘法器设计用于高速和低功率处理器
机译:低功耗肖特基TTL高速数字锁相环集成电路的设计