High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics

摘要

The main aim of the project is to improve the speed of the complex multiplier by using vedic mathematics. This 'Vedic Mathematics' is the name given to the ancient system of mathematics, or, to be precise, a unique technique of calculations based on simple rules and principles, with which any mathematical problem can done with the help of arithmetic, algebra, geometry or trigonometry can be solved. Traditionally complex multiplier provides less speed only, because it does not use Vedic Mathematics concept. By using 'Vedic Mathematics' concept we can skip carry propagation delay. The system is based on 16 Vedic sutras, in which we are using one kind of vedic sutra actually word-formulae describing natural ways of solving a whole range of mathematical problems.The main design features of the proposed system are the reconfigurability and flexibility. The proposed system is design using VHDL or Verilog HDL and is implemented through Xilinx ISE 9.1i navigator or modelsim6.0 softwares