Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs

摘要

New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O_2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Poly silicon thickness measurements have been taken to calculate etch rate and uniformity. Poly silicon wafers for each experimental condition were given different overetch times and SiO_2 losses were plotted against time, with the gradient yielding the SiO_2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.