Designing MOS/SOI Transistors for High Frequency and Low Voltage Applications

摘要

With the development of digital SOI technologies for portable communication systems [1, 2], high frequency modelization and design efforts are necessary to take into account some specific SOI effects. In this paper we evaluate the influence of the transistor design (process and geometry) on its frequency performances. We particularly investigate the influence of gate length and width, the ad junction of body ties to avoid floating body effects, and the DTMOS structure [3-5] for low voltage applications.