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首页> 外文期刊>Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures >InAlN/GaN heterostructure field-effect transistors on Fe-doped semi-insulating GaN substrates
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InAlN/GaN heterostructure field-effect transistors on Fe-doped semi-insulating GaN substrates

机译:掺铁半绝缘GaN衬底上的InAlN / GaN异质结构场效应晶体管

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摘要

InAlN/GaN heterostructure field-effect transistors (HFETs) have been grown and fabricated on Fe-doped semi-insulating c-plane GaN substrates. The problematic parasitic leakage caused by interface charge between the epitaxial layers and the GaN substrate as well as any adverse effect of the substrate surface damage caused by the mechanical chemical polish employed on the substrates has been circumvented by using a combination of inductively coupled plasma dry etching and in situ H2 etching. As a result, the current leakage for 100 μm separation mesa-to-mesa was reduced down to 3×10-9 A/mm at 10 V voltage bias for a 320 μm mesa pad width normal to the current flow direction and the corresponding GaN buffer resistivity was about 3.5×108 Ω cm. Owing to the good thermal conductivity of GaN substrates, the HFETs exhibit much less current degradation, compared to those on a sapphire substrate, at high drain biases. Likewise, the dc and pulsed I-V characteristics were reasonably similar, suggestive of negligible drain current lag. A dc saturation drain current density of 1.0 A/mm was achieved at zero gate bias. For HFETs with 1.1 μm gate length and 90 μm gate width, the maximum extrinsic dc transconductance was 275 mS/mm.
机译:InAlN / GaN异质结构场效应晶体管(HFET)已生长并制造在掺铁的半绝缘c面GaN衬底上。外延层与GaN衬底之间的界面电荷引起的有问题的寄生泄漏,以及由于对衬底进行机械化学抛光而导致的衬底表面损坏的任何不利影响,已经通过组合使用电感耦合等离子体干法刻蚀来解决。和原位H2蚀刻。结果,在垂直于电流流动方向的320μm台面焊盘宽度和相应的GaN情况下,在10 V电压偏置下,100μm台面至台面的电流泄漏降低至3×10-9 A / mm。缓冲电阻率约为3.5×108Ω·cm。由于GaN衬底具有良好的导热性,与蓝宝石衬底上的HFET相比,HFET在高漏极偏置下表现出的电流衰减要小得多。同样,直流和脉冲I-V特性也相当相似,表明漏极电流滞后可忽略不计。在零栅极偏置下实现了1.0 A / mm的dc饱和漏极电流密度。对于栅极长度为1.1μm,栅极宽度为90μm的HFET,最大外部直流跨导为275 mS / mm。

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