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首页> 外文期刊>Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures >Fabrication of on-chip fluidic channels incorporating nanopores using self-aligned double layer resist processing technique
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Fabrication of on-chip fluidic channels incorporating nanopores using self-aligned double layer resist processing technique

机译:使用自对准双层抗蚀剂加工技术制备包含纳米孔的芯片上流体通道

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摘要

The authors report on the development of a self-aligned double layer resist processing technique that allows incorporation of ion channel nanopores into on-chip microfluidic channels. The patterned positiveegative electron-beam resist double layer acts as a sacrificial template for the fabrication of on-chip fluidic channels and the nanopores. By controlling the resist dimensions, it was possible to tailor the shape of the on-chip fluidic channel and the nanopore dimensions. Using this technique, the authors demonstrated the fabrication of sub-10 nm nanopore arrays on 2 μm wide and 800 nm high on-chip fluidic channels. With further developments, it will be possible to have controllable on-chip nanopores with integrated nanofluidics.
机译:作者报告了自对准双层抗蚀剂加工技术的发展,该技术允许将离子通道纳米孔并入芯片上微流体通道。图案化的正/负电子束抗蚀剂双层充当制造芯片上流体通道和纳米孔的牺牲模板。通过控制抗蚀剂尺寸,可以调整芯片上流体通道的形状和纳米孔尺寸。使用这种技术,作者演示了在2μm宽和800 nm高的片上流体通道上制造10 nm以下的纳米孔阵列的过程。随着进一步的发展,将可能具有集成纳米流体的可控芯片上纳米孔。

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