20 nm polysilicon gate patterning and application in 36 nm complementar metal-oxide-semiconductor devices

摘要

Plasma etching with high selectivity and anisotropy for 20 nm poly-Si gate patterning on EOT of 1.4 nm gate oxynitride is developed in a Cl_2/HBr/O_2 gas mixture successfully. Direct write e-beam lithography is used for an SAL601 chemically amplified negative resist pattern. Using a combination of resist ashing and TEOS hard mask trimming process, sub-25 nm TEOS SiO_2 mask patterns are obtained in the control. Various gas mixtures based on Cl_2, HBr, and O_2 have been used to study the etching characteristics of poly-Si on EOT of 1.4 nm gate oxynitride. The O_2 content as well as HBr are very sensitive to etch rate, selectivity, and the protection of the sidewalls of polysilicon, owing to SiO_2-like film, SiO_xBr_y, formed on the etched surface confirmed by x-ray photoelectron spectroscopy. And the ratio of Cl_2 /HBr/O_2 in gas mixture is also tightly related to the etching profile. Using a four-step etching process under optimum conditions the selectivity of poly-Si to oxide is much higher than 500:1, in fact, after polysilicon etching the net deposition of oxide is observed, and no damage on the active area beside the gates for EOT of 1.4 nm gate oxide is observed, too. The etching profile of the 20 nm poly-Si gate pattern is perfectly vertical and an overall narrowing by an estimated 5 nm is observed for oxide masked poly-Si gate etching. The possible mechanism is discussed. This etching process combined with resist ashing and the TEOS hard mask trimming process are implemented successfully to the fabrication of high performance 36 nm gate length complementary metal-oxide-semiconductor (CMOS) devices and 42 nm gate length 32 frequency dividers with 57 stage/201 stage CMOS ring oscillators embedded, the EOT of gate oxynitrid is 1.4 nm, and very good results are obtained.